// syncgen.v // VGA video synchronous signal generator (base clock = 25[MHz]) `default_nettype none `include "my_const.v" `define H_PERIOD 799 `define H_DISP_END 639 `define H_FP_END 655 `define H_SYNC_END 751 `define V_PERIOD 524 `define V_DISP_END 479 `define V_FP_END 490 `define V_SYNC_END 492 module syncgen( input wire xtal, // 25[MHz] clock input wire reset_N, // active low reset output reg H_sync, // horizontal sync signal output reg V_sync, // vertical sync signal output wire [9:0] x_count, // horizontal position (0..639) output wire [9:0] y_count, // virtical position (0..479) output wire x_disp, // horizontal display area flag output wire y_disp); // virtical display area flag reg H_syncd; reg [9:0] clk_count; // horizontal clock counter reg [9:0] h_count; // virtical line counter // horizontal sync and x axis counter // basic counter always @(posedge xtal or negedge reset_N) begin if(!reset_N) begin clk_count <= 0; end else if(clk_count==`H_PERIOD) begin clk_count <= 0; end else begin clk_count <= clk_count + 1'b1; end end // X position count assign x_count = clk_count; // Hsync generator always @(posedge xtal or negedge reset_N) begin if(!reset_N) begin H_sync <= `OFF; end else if(clk_count==`H_FP_END) begin H_sync <= `ON; end else if(clk_count==`H_SYNC_END) begin H_sync <= `OFF; end end // horizontal display area signal (clk_count == 00_0000_0000 .. 10_0111_1111) assign x_disp = ~(clk_count[9] & (clk_count[8] | clk_count[7])); // virtical sync and y axis counter // basic counter always @(posedge xtal) begin H_syncd <= H_sync; end always @(posedge xtal or negedge reset_N) begin if(!reset_N) begin h_count <= 0; end else if(H_sync & ~H_syncd) begin if(h_count==`V_PERIOD) begin h_count <= 0; end else begin h_count <= h_count + 1'b1; end end end // Y position count assign y_count = h_count; // Vsync generator always @(posedge xtal or negedge reset_N) begin if(!reset_N) begin V_sync <= `OFF; end else if(h_count==`V_FP_END) begin V_sync <= `ON; end else if(h_count==`V_SYNC_END) begin V_sync <= `OFF; end end // vertical display area signal (h_count == 00_0000_0000 .. 01_1101_1111) assign y_disp = ~h_count[9] & (~& h_count[8:5]); endmodule