// fa.v // full adder `default_nettype none module fa( input wire a, b, cry_in, output wire sum, cry_out); wire sum_ab, cry_ha1, cry_ha2; ha HA1(a, b, sum_ab, cry_ha1); ha HA2(sum_ab, cry_in, sum, cry_ha2); assign cry_out = cry_ha1 | cry_ha2; endmodule