/* MAX2top2001.v -------- ロジック回路実験ボード・トップ・モジュール * * スライドスイッチ → 7セグメントLED 2桁表示 * * designed by Shinya KIMURA * * --------------------------- トランジスタ技術連載 BASICS (Digital) */ `default_nettype none module MAX2top( input wire XTAL, // X'tal OSC clock input wire MANCLK, // manual clock input wire DCLK, // 7-seg LED dynamic light on clock input wire RESET_N, // reset (active low) input wire [7:0] SLDSW, // slide switch input wire [1:0] RKT_PLS, // racket position pulse output wire [7:0] LED_N, // LED output wire [7:0] SEG_N, // 7-segment LED // [7:0] = {dot,g,f,e,d,c,b,a} output wire [3:0] SEGSEL_N, // 7-segment LED select // [3:0] = {left, .. , right} output wire RD, // VGA red output wire GR, // VGA green output wire BL, // VGA blue output wire H_SYNC_N, // horizontal sync. output wire V_SYNC_N, // vertical sync. output wire [1:0] RKT_TRG, // racket pulse trigger output wire SPKR); // speaker // internal signal (active high) wire [7:0] led; wire [7:0] seg; wire [3:0] segsel; wire [1:0] rkt_trg; wire H_sync; wire V_sync; wire rd, gr, bl; wire spkr; // active level conversion to positive logic assign LED_N = ~led; assign SEG_N = ~seg; assign SEGSEL_N = ~segsel; assign H_SYNC_N = ~H_sync; assign V_SYNC_N = ~V_sync; assign RD = rd; assign GR = gr; assign BL = bl; assign RKT_TRG = rkt_trg; assign SPKR = spkr; // additional internal signals wire [3:0] bcd; // core module instantiation or additional logic bcd7seg bcd7seg(bcd, seg[0], seg[1], seg[2], seg[3], seg[4], seg[5], seg[6]); assign bcd = DCLK ? SLDSW[7:4] : SLDSW[3:0]; assign segsel = DCLK ? 4'b0010 : 4'b0001; assign seg[7] = 1'b0; endmodule